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ISL9104, ISL9104A
Data Sheet December 23, 2008 FN6829.0
500mA 4.3MHz Low IQ High Efficiency Synchronous Buck Converter
The ISL9104, ISL9104A is a 500mA, 4.3MHz step-down regulator, which is ideal for powering low-voltage microprocessors in compact devices such as PDAs and cellular phones. It is optimized for generating low output voltages down to 0.8V. The supply voltage range is from 2.7V to 6V allowing the use of a single Li+ cell, three NiMH cells or a regulated 5V input. It has guaranteed minimum output current of 500mA. A high switching frequency of 4.3MHz pulse-width modulation (PWM) allows using small external components. Under light load condition, the device operates at low IQ skip mode with typical 20A quiescent current for highest light load efficiency to maximize battery life, and it automatically switches to fixed frequency PWM mode under heavy load condition. The ISL9104, ISL9104A includes a pair of low ON-resistance P-Channel and N-Channel internal MOSFETs to maximize system efficiency and minimize the external component count. 100% duty-cycle operation allows less than 300mV dropout voltage at 500mA. The ISL9104, ISL9104A offers internal digital soft-start, enable for power sequence, overcurrent protection and thermal shutdown functions. In addition, the ISL9104, ISL9104A offers a quick bleeding function that discharges the output capacitor when the IC is disabled. The ISL9104, ISL9104A is offered in a 1.6x1.6mm TDFN package. The complete converter occupies less than 0.5CM2.
Features
* High Efficiency Integrated Synchronous Buck Regulator with up to 93% Efficiency * 2.7V to 6.0V Supply Voltage * 4.3MHz PWM Switching Frequency * 500mA Guaranteed Output Current * 3% Output Accuracy Over-Temperature and Line for Fixed Output Options * 20A Quiescent Supply Current in Skip Mode * Less than 1A Logic Controlled Shutdown Current * 100% Maximum Duty Cycle for Lowest Dropout * Ultrasonic Switching Frequency at Skip Mode to Prevent Audible Frequency Noise (For ISL9104A Only) * Discharge Output Capacitor when Disabled * Internal Digital Soft-Start * Peak Current Limiting, Short Circuit Protection * Over-Temperature Protection * Chip Enable * Small 6 Pin 1.6mmx1.6mm TDFN Package * Pb-Free (RoHS Compliant)
Applications
* Single Li-ion Battery-Powered Equipment * Mobile Phones and MP3 Players * PDAs and Palmtops
Pinout
ISL9104, ISL9104A (6 LD 1.6x1.6 TDFN) TOP VIEW
VIN 1 EN 2 NC 3 6 SW 5 GND 4 FB
* WCDMA Handsets * Portable Instruments
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL9104, ISL9104A Ordering Information
PART NUMBER (Notes 1, 3) ISL9104IRUNZ-T Coming Soon ISL9104IRUJZ-T ISL9104IRUFZ-T Coming Soon ISL9104IRUDZ-T Coming Soon ISL9104IRUCZ-T ISL9104IRUBZ-T Coming Soon ISL9104IRUWZ-T ISL9104IRUAZ-T ISL9104AIRUNZ-T Coming Soon ISL9104AIRUJZ-T ISL9104AIRUFZ-T Coming Soon ISL9104AIRUDZ-T Coming Soon ISL9104AIRUCZ-T ISL9104AIRUBZ-T Coming Soon ISL9104AIRUWZ-T ISL9104AIRUAZ-T NOTES: 1. Please refer to TB347 for details on reel specifications. 2. For other output voltages, contact Intersil Marketing. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. PART MARKING K6 K7 K8 K9 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 M0 M1 OUTPUT VOLTAGE (V) (Note 2) 3.3 2.8 2.5 2.0 1.8 1.5 1.2 ADJ 3.3 2.8 2.5 2.0 1.8 1.5 1.2 ADJ TEMP RANGE (C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 PACKAGE (Pb-Free) 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN PKG DWG. # L6.1.6x1.6 L6.1.6x1.6 L6.1.6x1.6 L6.1.6x1.6 L6.1.6x1.6 L6.1.6x1.6 L6.1.6x1.6 L6.1.6x1.6 L6.1.6x1.6 L6.1.6x1.6 L6.1.6x1.6 L6.1.6x1.6 L6.1.6x1.6 L6.1.6x1.6 L6.1.6x1.6 L6.1.6x1.6 ULTRASONIC FUNCTION NO NO NO NO NO NO NO NO YES YES YES YES YES YES YES YES
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ISL9104, ISL9104A
Absolute Maximum Ratings
VIN, EN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FB to GND (for adjustable version) . . . . . . . . . . . . . . . FB to GND (for fixed output version) . . . . . . . . . . . . . . -0.3V to 6.5V -1.5V to 6.5V -0.3V to 2.7V -0.3V to 3.6V
Thermal Information
Thermal Resistance (Typical, Note 4) JA (C/W) 1.6x1.6 TDFN Package . . . . . . . . . . . . . . . . . . . . . 160 Junction Temperature Range. . . . . . . . . . . . . . . . . .-40C to +125C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . 2.7V to 6.0V Load Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .up to 500mA Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-40C to +85C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTE: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379.
Electrical Specifications
Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and the typical specifications are measured at the following conditions: TA = +25C, VIN = VEN = 3.6V, L = 1.0H, C1 = 4.7F, C2 = 4.7F, IOUT = 0A (see "Typical Applications" on page 8). Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER SUPPLY Undervoltage Lockout Threshold (UVLO) UVLO Hysteresis Quiescent Supply Current (for ISL9104 adjustable output voltage only) Quiescent Supply Current (for ISL9104A adjustable output only) Quiescent Supply Current (for ISL9104A 1.5V fixed output) Shut Down Supply Current OUTPUT REGULATION FB Voltage Accuracy (for adjustable output only) FB Voltage FB Bias Current (for adjustable output only) Output Voltage Accuracy (for fixed output voltage only) Line Regulation Load Regulation SW P-Channel MOSFET ON-Resistance
VUVLO
TA = +25C, Rising
50
2.5 150 20 32 84
2.7 34 45
V mV A A A
IVIN1 IVIN2
In skip mode, no load at the output, no switch, VIN = 6.0V In skip mode, no load at the output, no switch, VIN = 6.0V In skip mode, no load at the output, VIN = 6.0V
-
ISD
VIN = 6.0V, EN = LOW
-
0.05
1
A
TA = 0C to +85C
-2 -2.5
0.8
+2 +2.5
% % V
VFB IFB VFB = 0.75V PWM Mode VIN = VO + 0.5V to 6V (minimal 2.7V) VIN =3.6V, IO = 150mA to 500mA -3 -
5
100 3
nA % %/V %/mA
0.2 0.0009
-
VIN = 3.6V, IO = 200mA VIN = 2.7V, IO = 200mA
-
0.45 0.55 0.4 0.5 100
0.6 0.72 0.52 0.65

N-Channel MOSFET ON-Resistance
VIN = 3.6V, IO = 200mA VIN = 2.7V, IO = 200mA
N-Channel Bleeding MOSFET ON-Resistance P-Channel MOSFET Peak Current Limit Maximum Duty Cycle IPK VIN = 3.6V 0.75 -
1.00 100
1.25 -
A %
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ISL9104, ISL9104A
Electrical Specifications
Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and the typical specifications are measured at the following conditions: TA = +25C, VIN = VEN = 3.6V, L = 1.0H, C1 = 4.7F, C2 = 4.7F, IOUT = 0A (see "Typical Applications" on page 8). Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) SYMBOL TEST CONDITIONS MIN TYP 0.01 fS VIN = 3.6V, TA = -20C to +85C 3.6 4.3 65 1.0 MAX 2 4.9 UNITS A MHz ns ms
PARAMETER SW Leakage Current PWM Switching Frequency SW Minimum On-Time Soft-Start-Up Time EN Logic Input Low Logic Input High Logic Input Leakage Current Thermal Shutdown Thermal Shutdown Hysteresis
1.4 -
0.1 130 30
0.4 1 -
V V A C C
Typical Operating Performance
100 90 80 EFFICIENCY (%) EFFICIENCY (%) 70 60 50 40 30 20 10 0 0 0.1 0.2 0.3 LOAD CURRENT (A) 0.4 0.5 VIN = 3.8V VIN = 4.9V VIN = 2.7V 100 90 80 70 60 50 40 30 20 10 0 0 0.1 0.2 0.3 LOAD CURRENT (A) 0.4 0.5 VIN = 3.5V VIN = 4.5V
VIN = 5.5V
FIGURE 1. EFFICIENCY vs LOAD CURRENT (VOUT = 1.5V)
FIGURE 2. EFFICIENCY vs LOAD CURRENT (VOUT = 2.5V)
30 QUIESCENT CURRENT (A)
1.630 1.625
25
T = +85C T = +25C 1.620 VO (V) 1.615 1.610 LOAD CURRENT RISING
20
15 1.605 T = -45C 10 2.70 3.25 3.80 4.35 4.90 5.45 6.00 1.600 0 100 LOAD CURRENT FALLING
INPUT VOLTAGE (V)
200 300 IOUT (mA)
400
500
FIGURE 3. INPUT QUIESCENT CURRENT vs VIN (VOUT = 2.5V)
FIGURE 4. OUTPUT VOLTAGE vs LOAD CURRENT (VIN = 3.6V, VOUT = 1.6V)
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ISL9104, ISL9104A Typical Operating Performance (Continued)
2.505 2.500 LOAD CURRENT RISING 2.495 VO (V) 2.490 2.485 2.480 2.475 0 LOAD CURRENT FALLING 200mA/DIV 5V/DIV 100 200 300 IOUT(mA) 400 500 IL EN 1V/DIV VOUT 5V/DIV VSW
FIGURE 5. OUTPUT VOLTAGE vs LOAD CURRENT (VIN = 4.0V, VOUT = 2.5V)
FIGURE 6. SOFT-START TO PFM MODE (VIN = 3.6V, VOUT = 1.5V, IOUT = 0.001mA)
5V/DIV
5V/DIV VSW
VSW
1V/DIV VOUT 500mA/DIV IL 5V/DIV EN
2V/DIV VOUT 200mA/DIV IL 5V/DIV EN
FIGURE 7. SOFT-START TO PWM MODE (VIN = 3.6V, VOUT = 1.5V, IOUT = 500mA)
FIGURE 8. SOFT-START TO PFM MODE (VIN = 3.6V, VOUT = 2.5V, IOUT = 0.001mA)
5V/DIV
VSW
5V/DIV
VSW
20mV/DIV VOUT (AC COUPLED)
20mV/DIV VOUT (AC COUPLED)
20mA/DIV Io 20mA/DIV Io
FIGURE 9. LOAD TRANSIENT IN PFM MODE (VIN = 3.6V, VOUT = 1.5V, 5mA TO 30mA)
FIGURE 10. LOAD TRANSIENT IN PFM MODE (VIN = 3.6V, VOUT = 1.5V, 30mA TO 5mA)
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ISL9104, ISL9104A Typical Operating Performance (Continued)
5V/DIV
VSW
5V/DIV
VSW
20mV/DIV VOUT (AC COUPLED)
20mV/DIV VOUT (AC COUPLED)
20mA/DIV
Io
20mA/DIV
Io
FIGURE 11. LOAD TRANSIENT IN PFM MODE (VIN = 3.6V, VOUT = 2.5V, 5mA TO 30mA)
FIGURE 12. LOAD TRANSIENT IN PFM MODE (VIN = 3.6V, VOUT = 2.5V, 30mA TO 5mA)
5V/DIV
VSW
5V/DIV
VSW
50mV/DIV VOUT (AC COUPLED)
50mV/DIV
VOUT (AC COUPLED)
200mA/DIV
Io
200mA/DIV
Io
FIGURE 13. LOAD TRANSIENT FROM PFM TO PWM MODE (VIN = 3.6V, VOUT = 1.5V, 5mA TO 300mA)
FIGURE 14. LOAD TRANSIENT FROM PWM TO PFM MODE (VIN = 3.6V, VOUT = 1.5V, 300mA TO 5mA)
5V/DIV
VSW
5V/DIV VSW
50mV/DIV VOUT (AC COUPLED)
50mV/DIV VOUT (AC COUPLED)
200mA/DIV Io
200mA/DIV
Io
FIGURE 15. LOAD TRANSIENT FROM PFM TO PWM MODE (VIN = 3.6V, VOUT = 2.5V, 5mA TO 300mA)
FIGURE 16. LOAD TRANSIENT FROM PWM TO PFM MODE (VIN = 3.6V, VOUT = 2.5V, 300mA TO 5mA)
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FN6829.0 December 23, 2008
ISL9104, ISL9104A Typical Operating Performance (Continued)
5V/DIV
VSW
5V/DIV VSW
20mV/DIV VOUT (AC COUPLED)
20mV/DIV VOUT
500mA/DIV
Io
500mA/DIV
Io
FIGURE 17. LOAD TRANSIENT IN PWM MODE (VIN = 3.6V, VO = 1.5V, 200mA TO 500mA)
FIGURE 18. LOAD TRANSIENT IN PWM MODE (VIN = 3.6V, VO = 1.5V, 500mA TO 200mA)
5V/DIV VSW
5V/DIV VSW
20mV/DIV VOUT (AC COUPLED)
20mV/DIV VOUT (AC COUPLED)
500mA/DIV Io 500mA/DIV Io
FIGURE 19. LOAD TRANSIENT IN PWM MODE (VIN = 3.6V, VO = 2.5V, 200mA TO 500mA)
FIGURE 20. LOAD TRANSIENT IN PWM MODE (VIN = 3.6V, VO = 2.5V, 500mA TO 200mA)
Pin Descriptions
VIN
Input supply voltage. Typically connect a 4.7F ceramic capacitor to ground.
FB
Buck converter output feedback pin. For adjustable output version, its typical value is 0.8V and connect it to the output through a resistor divider for desired output voltage; for fixed output version, directly connect this pin to the converter output.
NC
No connect, leave it floating.
EN
Regulator enable pin. Enable the device when driven to high. Shut down the chip and discharge output capacitor when driven to low. Do not leave this pin floating.
SW
Switching node connection. Connect to one terminal of inductor.
GND
Ground connection.
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FN6829.0 December 23, 2008
ISL9104, ISL9104A Typical Applications
ISL9104, ISL9104A ADJUSTABLE OUTPUT L 1.0H VIN C1 4.7F ENABLE EN DISABLE GND FB R2 100k SW C2 4.7F R1 100k C3 47pF
OUTPUT 500mA
INPUT: 2.7V TO 6V
ISL9104, ISL9104A FIXED OUTPUT L 1.0H VIN C1 4.7F SW C2 4.7F
INPUT: 2.7V TO 6V
OUTPUT 500mA
ENABLE EN DISABLE GND FB
FIGURE 21. TYPICAL APPLICATIONS DIAGRAM
Note: For adjustable output version, the internal feedback resistor divider is disabled and the FB pin is directly connected to the error amplifier.
PARTS
L C1, C2 C3 R1, R2
DESCRIPTION
Inductor Input and output capacitor Capacitor Resistor
MANUFACTURERS
KEMET Murata KEMET Various
PART NUMBER
LB3218-T1R0MK GRM188R60J475KE19D C0402C470J5GACTU -
SPECIFICATIONS
1.0H/1.0A/60m 4.7F/6.3V, X5R 47pF/50V 100k, SMD, 1%
SIZE
3.2mmx1.8mmx1.8mm 0603 0402 0402
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FN6829.0 December 23, 2008
ISL9104, ISL9104A Block Diagram
SHUTDOW N SO SO FTFT STA START RT O S C IL L A T O R + EN BANDGAP VREF EAMP + COMP SHUTDOW N
V IN
P W M /P F M L O G IC CONTROLLER P R O T E C T IO N D R IV E R
SW
SLO PE COMP *N O T E
X GND
FB
B L E E D IN G FET 100 + + OCP SCP VREF3 + + S K IP VREF2 VREF1 CSA
Z E R O -C R O S S S E N S IN G *N O T E : F O R F IX E D O U T P U T O P T IO N S O N L Y
NOTE: For Adjustable output version, the internal feedback resistor divider is disabled and the FB pin is directly connected to the error amplifier. FIGURE 22. FUNCTIONAL BLOCK DIAGRAM
Theory of Operation
The ISL9104, ISL9104A is a step-down switching regulator optimized for battery-powered handheld applications. The regulator operates at typical 4.3MHz fixed switching frequency under heavy load condition to allow small external inductor and capacitors to be used for minimal printed-circuit board (PCB) area. At light load, the regulator can automatically enter the skip mode (PFM mode) to reduce the switching frequency to minimize the switching loss and to maximize the battery life. The quiescent current under skip mode under no load and no switch condition is typically only 20A. The supply current is typically only 0.05A when the regulator is disabled.
control reference for the current loops comes from the Error Amplifier (EAMP) of the voltage loop. The PWM operation is initialized by the clock from the oscillator. The P-Channel MOSFET is turned on at the beginning of a PWM cycle and the current in the P-Channel MOSFET starts ramping up. When the sum of the CSA output and the compensation slope reaches the control reference of the current loop, the PWM comparator COMP sends a signal to the PWM logic to turn off the P-Channel MOSFET and to turn on the N-Channel MOSFET. The N-MOSFET remains on till the end of the PWM cycle. Figure 23 shows the typical operating waveforms during the normal PWM operation. The dotted lines illustrate the sum of the slope compensation ramp and the CSA output.
PWM Control Scheme
The ISL9104, ISL9104A uses the peak-current-mode pulse-width modulation (PWM) control scheme for fast transient response and pulse-by-pulse current limiting. Figure 22 shows the circuit functional block diagram. The current loop consists of the oscillator, the PWM comparator COMP, current sensing circuit, and the slope compensation for the current loop stability. The current sensing circuit consists of the resistance of the P-Channel MOSFET when it is turned on and the Current Sense Amplifier (CSA). The
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ISL9104, ISL9104A
During the 16-consecutive cycles, the inductor current could be negative. The counter is reset to zero when the sensed current flowing through SW node does not cross zero during any cycle within the 16-consecutive cycles. Once ISL9104, ISL9104A enters the skip mode, the pulse modulation starts being controlled by the SKIP comparator shown in Figure 22. Each pulse cycle is still synchronized by the PWM clock. The P-Channel MOSFET is turned on at the rising edge of clock and turned off when its current reaches ~20% of the peak current limit. As the average inductor current in each cycle is higher than the average current of the load, the output voltage rises cycle over cycle. When the output voltage is sensed to reach 1.5% above its nominal voltage, the P-Channel MOSFET is turned off immediately and the inductor current is fully discharged to zero and stays at zero. The output voltage reduces gradually due to the load current discharging the output capacitor. When the output voltage drops to the nominal voltage, the P-Channel MOSFET will be turned on again, repeating the previous operations. The regulator resumes normal PWM mode operation when the output voltage is sensed to drop below 1.5% of its nominal voltage value.
vEAMP vCSA d iL vOUT
FIGURE 23. PWM OPERATION WAVEFORMS
The output voltage is regulated by controlling the reference voltage to the current loop. The bandgap circuit outputs a 0.8V reference voltage to the voltage control loop. The feedback signal comes from the FB pin. The soft-start block only affects the operation during the start-up and will be discussed separately in "Soft-Start" on page 11. The EAMP is a transconductance amplifier, which converts the voltage error signal to a current output. The voltage loop is internally compensated by a RC network. The maximum EAMP voltage output is precisely clamped to the bandgap voltage.
Enable
The enable (EN) pin allows user to enable or disable the converter for purposes such as power-up sequencing. With EN pin pulled to high, the converter is enabled and the internal reference circuit wakes up first and then the soft start-up begins. When EN pin is pulled to logic low, the converter is disabled, both P-Channel MOSFET and N-Channel MOSFETS are turned off, and the output capacitor is discharged through internal discharge path.
Skip Mode (PFM Mode)
Under light load condition, ISL9104, ISL9104A automatically enters a pulse-skipping mode to minimize the switching loss by reducing the switching frequency. Figure 24 illustrates the skip mode operation. A zero-cross sensing circuit (as shown in Figure 22) monitors the current flowing through SW node for zero crossing. When it is detected to cross zero for 16-consecutive cycles, the regulator enters the skip mode.
16 CYCLES
CLOCK 20% PEAK CURRENT LIMIT IL
0 1.015*VOUT_NOMINAL
VOUT VOUT_NOMINAL
FIGURE 24. SKIP MODE OPERATION WAVEFORMS
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ISL9104, ISL9104A
Overcurrent Protection
The overcurrent protection is provided on ISL9104, ISL9104A when overload condition happens. It is realized by monitoring the CSA output with the OCP comparator, as shown in Figure 22. When the current at P-Channel MOSFET is sensed to reach the current limit, the OCP comparator is trigged to turn off the P-Channel MOSFET immediately. peak-to-peak inductor current ripple can be expressed in Equation 1:
VO V O * 1 - --------- V IN I = -------------------------------------L * fS
(EQ. 1)
Short-Circuit Protection
ISL9104, ISL9104A has a Short-Circuit Protection (SCP) comparator, which monitors the FB pin voltage for output short-circuit protection. When the output voltage is sensed to be lower than a certain threshold, the SCP comparator reduces the PWM oscillator frequency to a much lower frequency to protect the IC from being damaged.
In Equation 1, usually the typical values can be used but to have a more conservative estimation, the inductance should consider the value with worst case tolerance; and for switching frequency fS, the minimum fS from the "Electrical Specifications" table on page 3 can be used. To select the inductor, its saturation current rating should be at least higher than the sum of the maximum output current and half of the delta calculated from Equation 1. Another more conservative approach is to select the inductor with the current rating higher than the P-Channel MOSFET peak current limit. Another consideration is the inductor DC resistance since it directly affects the efficiency of the converter. Ideally, the inductor with the lower DC resistance should be considered to achieve higher efficiency. Inductor specifications could be different from different manufacturers so please check with each manufacturer if additional information is needed. For the output capacitor, a ceramic capacitor can be used because of the low ESR values, which helps to minimize the output voltage ripple. A typical value of 4.7F/6.3V ceramic capacitor should be enough for most of the applications and the capacitor should be X5R or X7R.
Undervoltage Lockout (UVLO)
When the input voltage is below the Undervoltage Lock Out (UVLO) threshold, ISL9104, ISL9104A is disabled.
Soft-Start
The soft-start feature eliminates the inrush current during the circuit start-up. The soft-start block outputs a ramp reference to both the voltage loop and the current loop. The two ramps limit the inductor current rising speed as well as the output voltage speed so that the output voltage rises in a controlled fashion.
Low Dropout Operation
The ISL9104, ISL9104A features low dropout operation to maximize the battery life. When the input voltage drops to a level that ISL9104, ISL9104A can no longer operate under switching regulation to maintain the output voltage, the P-Channel MOSFET is completely turned on (100% duty cycle). The dropout voltage under such condition is the product of the load current and the ON-resistance of the P-Channel MOSFET. Minimum required input voltage VIN under this condition is the sum of output voltage plus the voltage drop cross the inductor and the P-Channel MOSFET switch.
Input Capacitor Selection
The main function for the input capacitor is to provide decoupling of the parasitic inductance and to provide filtering function to prevent the switching current from flowing back to the battery rail. A 4.7F/6.3V ceramic capacitor (X5R or X7R) is a good starting point for the input capacitor selection.
Thermal Shut Down
The ISL9104, ISL9104A provides built-in thermal protection function. The thermal shutdown threshold temperature is +130C (typ) with a 30C (typ) hysteresis. When the internal temperature is sensed to reach +130C, the regulator is completely shut down and as the temperature drops to +100C (typ), the ISL9104, ISL9104A resumes operation starting from the soft-start.
Output Voltage Setting Resistor Selection
For ISL9104, ISL9104A adjustable output option, the voltage resistors, R1 and R2, as shown in Figure 21, set the desired output voltage values. The output voltage can be calculated using Equation 2:
R 1 V O = V FB * 1 + ------ R 2
(EQ. 2)
Applications Information
Inductor and Output Capacitor Selection
To achieve better steady state and transient response, ISL9104, ISL9104A typically uses a 1.0H inductor. The
where VFB is the feedback voltage (typically it is 0.8V). The current flowing through the voltage divider resistors can be calculated as VO/(R1 + R2), so larger resistance is desirable to minimize this current. On the other hand, the FB pin has leakage current that will cause error in the output voltage setting. The leakage current has a typical value of 0.1A. To
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ISL9104, ISL9104A
minimize the accuracy impact on the output voltage, select the R2 no larger than 200k. For adjustable output versions, C3 (shown in Figure 21) is highly recommended for improving stability and achieving better transient response. Table 1 provides the recommended component values for some output voltage options.
TABLE 1. RECOMMENDED IISL9104, ISL9104A ADJUSTABLE OUTPUT VERSION CIRCUIT CONFIGURATION vs VOUT VOUT (V)
0.8 1.0 1.2 1.5 1.8 2.5 2.8 3.3
Layout Recommendation
The PCB layout is a very important converter design step to make sure the designed converter works well, especially under the high current high switching frequency condition. For ISL9104, ISL9104A, the power loop is composed of the output inductor L, the output capacitor COUT, the SW pin and the PGND pin. It is necessary to make the power loop as small as possible and the connecting traces among them should be direct, short and wide; the same type of traces should be used to connect the VIN pin, the input capacitor CIN and its ground. The switching node of the converter, the SW pin, and the traces connected to this node are very noisy, so keep the voltage feedback trace and other noise sensitive traces away from these noisy traces. The input capacitor should be placed as close as possible to the VIN pin. The ground of the input and output capacitors should be connected as close as possible as well. In addition, a solid ground plane is helpful for EMI performance.
L (H)
1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0
C2 (F)
4.7 4.7 4.7 4.7 4.7 4.7 4.7 4.7
R1 (k)
0 44.2 80.6 84.5 100 100 100 102
C3 (pF)
N/A 100 47 47 47 47 47 47
R2 (k)
N/A 178 162 97.6 80.6 47.5 40.2 32.4
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12
FN6829.0 December 23, 2008
ISL9104, ISL9104A
Package Outline Drawing
L6.1.6x1.6
6 LEAD ULTRA THIN DUAL FLAT NO-LEAD COL PLASTIC PACKAGE (UTDFN COL) Rev 1, 11/07
2X 1.00 1.60 6 PIN 1 INDEX AREA A PIN #1 INDEX AREA 6 B 1 4X 0.50 3 5X 0 . 40 0 . 1 1X 0.5 0.1
1.60
(4X)
0.15 6
TOP VIEW BOTTOM VIEW
4 0.10 M C A B 4 0.25 +0.05 / -0.07
( 6X 0 . 25 )
SEE DETAIL "X" ( 1X 0 .70 ) 0 . 55 MAX
0.10 C
C
BASE PLANE (1.4 )
SEATING PLANE 0.08 C
SIDE VIEW
0 . 2 REF
C
( 5X 0 . 60 )
0 . 00 MIN. 0 . 05 MAX. ( 4X 0 . 5 )
TYPICAL RECOMMENDED LAND PATTERN DETAIL "X"
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
13
FN6829.0 December 23, 2008

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